Effect of Delay Estimation on Placement of Standard Cells in TDP

In the physical designing of the chip, placement is one of the most important steps in the design flow. As the feature size is reducing timing driven placement (TDP) seems to be more promising technique, proper estimation of delay value plays a vital role in deriving the optimized placement results in such technique. In this paper we, bring out the different cell delay estimation method ranging from traditional method of estimation i.e. regression and also interpolation / extrapolation used in NLDM (Non-Linear Delay Model) to find the exact value of entries which are not present in the lookup table. And the way in which, delay estimation will affect the placement scheme of the standard cells of the design which has to meet the timing requirements of the design (STA). This paper talks about different approaches to meet the timing requirement in order to arrange the logic cells in more efficient way in case of timing driven placement (TDP).